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8237A-5 Direct Memory Access (DMA) controller
The 8237 provides four independent channels for fast data
transfer of up to 64K between devices and memory, or
memory to memory (using two channels). Memory-to-memory
transfer is not supported on the PC.
The DMA controller accomplishes data movement using one-sixth
of the clock cycles needed by the 8088. The Technical Reference
manual does not document the inner working of the 8237, or
contain instructions for its use, as it is not normally
accessible from user programs, and its correct operation
is crucial to system activities. See Intel Microprocessor
and Peripheral Handbook, for specifications.
Channel 0 has highest priority for operation, with channel 3
having the lowest priority DMA channels 1-3 are present on I/O
bus to the expansion slots. The read-cycle created by channel
0 is also present on the I/O bus.
See Also: 000 001 002 003 004 005 006 007 008 009 00A
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